1. Field of the Invention
The present invention relates to a phase-locked loop circuit and a semiconductor integrated circuit having the phase-locked loop circuit, and more particularly, to a phase-locked loop circuit that permits a reduction of circuit size.
2. Description of the Related Art
In recent years, in accordance with the operating speeds of CPUs getting faster and faster, high speed operation has come to be demanded of memory circuits (for example, DRAMs) and other peripheral circuits. In order to prevent timing errors from occurring between the circuits in high speed operation, it is practiced, for example, to mount a phase-locked loop (PLL) circuit to synchronize the memory circuits and other peripheral circuits to an external clock, thus synchronizing each circuit to the CPU clock.
Namely, in the prior art, a PLL circuit that generates a waveform using a voltage-controlled oscillator (VCO) has been used as the phase-locked loop circuit. However, the VCO has the problems of increased circuit size and increased power consumption. Further, the PLL circuit involves such problems as degraded precision due to noise occurring in analog portions.
In view of this situation, a delay-locked loop (DLL) involving a delay stage has been attracting attention as a circuit capable of providing signal synchronization at high operating frequency. The DLL, however, has the problem that the circuit size is increased because of the large number of logic gates (for example, inverters) required to construct the delay stage.
This has therefore lead to the problem that it is difficult to reduce the power consumption and the size of the entire circuit because the phase-locked loop circuit occupies a large portion of the entire circuit.